Deserializer, semiconductor device, electronic device, and data transmission system

ABSTRACT

A serial-to-parallel converter ( 130 ) samples serial data DA 1  comprising a first data string, which includes one or more unit data strings each including a predetermined number of bits (00XXX . . . XXX) and which is input after a synchronization period, in accordance with a clock signal CL 1  which has been used to generate the serial data by converting original parallel data into serial form, thereby converting the serial data to parallel data from one unit data string to another. Signal generation means ( 140 ) generates a synchronization signal corresponding to a synchronization period in accordance with the serial data DA 1  and the clock signal CL 1 . The serial data includes a second data string (1100 . . . 000) which appears in each synchronization period and which includes one or more unit data strings having a predetermined bit pattern. If the signal generation means ( 140 ) detects a unit data string (11000 . . . 000) in the second data string, it generates a synchronization signal. In accordance with the synchronization signal, the serial-to-parallel converter ( 130 ) detects the start position of the unit data string in the first data string.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a serial-to-parallel conversionapparatus, a semiconductor device, an electronic device, and a datatransmission system, and more particularly to an apparatus fortransmitting digital image information from an information processingapparatus to a device such as a liquid crystal display, a large-sizehigh-resolution flat panel display, a liquid crystal projector, or amulti-display system.

2. Description of Related Art

A data transmission system for transmitting image information such asthat shown in FIG. 16 is known in the art. In such a system, it is knownto use one or more pairs of wires as transmission means for transmittingdigital image information to a display device. This technique is calledLVDS (low voltage differential signal) transmission.

In the data transmission system shown in FIG. 16, data is transmittedfrom one information processing apparatus 500 to another informationprocessing apparatus 600 via an LVDS cable.

In a transmitting apparatus, parallel data 513 such as image informationoutput from the information processing apparatus 500 at the transmittingend is converted into serial data 514 by a parallel-to-serial converter520 in accordance with a clock signal CL 511 produced by a PLL 530 byway of multiplying the frequency of a dot clock signal CL 510.

The resultant serial data 514 is transmitted together with a clocksignal CL 512 similar to the dot clock signal CL 510 via drivers 540(540-1, 540-2, . . . ), a cable 560, and receivers 630 (630-1, 630-2, .. . ).

In accordance with a clock signal CL 602 generated by a PLL 620 by wayof multiplying the frequency of a clock signal CL 601 similar to theclock signal CL 512, a serial-to-parallel converter 610 converts theserial data 604 to parallel data 605 and supplies the resultant paralleldata 605 to the information processing apparatus 600.

In the case where the cable comprising one or more pairs of wires, thedot clock signal CL 510 (512, 601, 603) and the coded serial data 514(604) are transmitted, while in the receiving apparatus the clock signalCL 602 is generated by multiplying the frequency of the dot clock signalCL 601 and the serial data is reconverted to parallel data in accordancewith the obtained clock signal CL 602.

When serial data is converted to parallel data, it is required to detectboundaries (start positions of respective data strings) between twoadjacent data strings of the serial data. As can be seen from FIG. 18,information used to detect the boundaries is given by the clock signalCL 601 (CL 510, CL 512). Because one cycle of the clock signal CL 601corresponds to the length of one unit data string, the timing of eachrising edge (or falling edge) of the clock signal CL 601 has aparticular relation with the start position of a data string of theserial data 604. Therefore, the start position of each data string ofthe serial data 604 can be detected by detecting a rising edge (orfalling edge) of the clock signal CL 601, and thus it is possible toconvert serial data to parallel data without producing a bit positionerror.

However, the dot clock signal CL 510 output from the informationprocessing apparatus 500 often has large jitter which affects extractionof the clock signal or multiplication of the dot clock signal performedin the receiving apparatus and thus causes a failure in conversion toparallel data or in reproduction of data.

That is, as shown in FIGS. 16 and 18, when parallel data (A0), . . . ,(Ak) are input to the parallel-to-serial converter 520 via parallel datainput terminals Txin0-Txink, the parallel-to-serial converter 520sequentially samples the parallel data (A0), . . . , (Ak) from data todata in synchronization with the clock signal CL 511 generated by meansof frequency multiplication thereby converting them into serial data (A0. . . Ak).

The resultant serial data (A0 . . . Ak) is output together with the dotclock signal CL510 from the driver 540 and transmitted via the LVDScable 560.

The serial data (A0 . . . Ak) 604 is then input, as shown in FIGS. 16and 18, to the serial-to-parallel converter 610 via the serial datainput terminal Rxin and sampled in synchronization with the clock signalCL602 generated by way of frequency multiplication.

As described above, because the start position of the serial data (A0 .. . Ak) can be detected from the timing of a rising edge (or fallingedge) of the clock signal CL601, it is possible to output the paralleldata (A0), . . . , (Ak) so that A0 corresponds to Rxout0 and A1corresponds to Rxout1.

If jitter occurs in the clock signal CL510, a phase difference occursbetween the clock signal CL511 multiplied in the transmitting apparatusand the clock signal CL602 multiplied in the receiving apparatus, asshown in FIG. 19, and thus the serial-to-parallel converter 610 cannotperform a correct conversion upon the parallel data converted intoserial form by the parallel-to-serial converter 520. The term “jitter”is generally used to describe a waveform disturbance such as that shownin FIG. 19.

More specifically, referring to the timing chart of FIG. 17 illustratingthe relationship among the serial data 604, the parallel data 605, andCL602 (multiplied signal) in the serial-to-parallel converter 610,jitter causes a deviation between the timing of the clock signal CL601or 602 and the start position of the nth data string of the serial data.Such a deviation can cause incorrect detection of a boundary betweenadjacent data strings (the start position of a data string) of theserial data.

The major cause of the above problem is in that the serial-to-parallelconverter 610 performs the converting operation in synchronization withthe clock signal CL602 multiplied by the PLL 620.

In the parallel-to-serial converter 520, the clock signal 511 isgenerated by the PLL 520 by way of frequency multiplication, while inthe serial-to-parallel converter 610 the clock signal 602 is generatedby the PLL 620 by way of frequency multiplication. Therefore, if theclock signal 510 includes jitter, a timing deviation between the clocksignals 511 and 602 occurs as shown in FIG. 19. When there is suchjitter, if the serial data 604 generated on the basis of the multipliedclock signal 511 is sampled in synchronization with the clock signal602, the resultant parallel data may be incorrect.

The phase error generated by the jitter can cause an incorrect detectionof a signal level. For example, a signal level which should bedetermined as a low level may be incorrectly determined as a high level.As a result, it becomes difficult or even impossible to correctly readthe content of data. That is, because the serial-to-parallel conversionis performed on the basis of the out-of-synchronization clock signal,data may be incorrectly converted into parallel form. For example, datawhich should be converted to R0, G0, and B0 may be incorrectly convertedto G0, B0, and R1.

Furthermore, in order that a VCO (voltage controlled oscillator) of thePLL can operate in a stable fashion, it is required that the voltage ofa power supply should be stable enough. However, in general,fluctuations of the voltage of the power supply occur owing to noise ina logic circuit or the like, and thus the operation of the PLL becomeunstable. For the above reasons, use of two PLLs, one in thetransmitting apparatus and the other in the receiving apparatus, resultsin a reduction in a margin for correct reception of data. Furthermore,in order that each PLL operates in a stable fashion, it is required thatthe power supply voltage should be stabilized over the entire apparatus.This results in an increase in cost.

SUMMARY OF THE INVENTION

In view of the above problems, it is an object of the present inventionto provide a serial-to-parallel conversion apparatus, a semiconductordevice, an electronic device, and a data transmission system, in whichserial data is correctly converted to parallel data without encounteringa conversion timing error in a serial-to-parallel converter therebymaking it possible to correctly display an image at a receiving end.

The present invention provides:

(1) A serial-to-parallel conversion apparatus comprising: dataconversion means (data computer) for sampling a first data string in theform of serial data, which includes one or more unit data strings eachincluding a predetermined number of bits and which is input after asynchronization period, in accordance with a clock signal which has beenused to generate the serial data by converting original parallel datainto serial form, thereby converting the serial data to parallel datafrom one unit data string to another; and signal generation means(signal generator) for generating a synchronization signal correspondingto the synchronization period, on the basis of the serial data, wherein:the serial data includes a second data string for synchronizationdetection within the synchronization period, the second data stringincluding one or more unit data strings each having a predetermined bitpattern; the signal generation means generates the synchronizationsignal when detecting the unit data string in the second data string;and the data conversion means detects the start position of the unitdata string in the first data string on the basis of the synchronizationsignal.

In the apparatus according to (1), serial data is converted by the dataconversion means to parallel data. The sampling clock signal used hereinto perform the conversion of the serial data into the parallel data isthe same sampling clock signal as that used in conversion from originalparallel data to that serial data. Therefore, even if the clock signalused in the parallel-to-serial conversion includes jitter, no timingerror occurs in the serial-to-parallel-conversion because the same clocksignal is used. Furthermore, in the present invention, instead ofgenerating a sampling clock signal on the basis of a reference clocksignal (such as a dot clock signal), the synchronization signal isgenerated by the signal generation means by detecting the second datastring in the serial data. On the basis of this synchronization signal,the position of a unit data string which appears first in the first datastring is detected thereby determining the start timing of outputtingthe parallel data.

The present invention also provides serial-to-parallel conversionapparatus described below in (2) to (8).

(2) A serial-to-parallel conversion apparatus according to (1), whereinthe bit pattern of the unit data string in the second data string is aunique pattern different from any bit pattern that unit data strings inthe first data string can have.

In the apparatus according to (2), it is possible to prevent a unit datastring in the first data string from being detected incorrectly as adata string in the second data string.

(3) A serial-to-parallel conversion apparatus according to (2), whereinthe signal generation means (data storage device) includes data stringdetection means, to which the clock signal and the serial data areinput, for detecting the unit data string in the second data string fromthe serial data thereby outputting the synchronization signal.

In the apparatus according to (3), it becomes possible to output asynchronization signal each time a unit data string in the second datastring is detected from the serial data. Because the unit data string inthe second data string is generated periodically, the synchronizationsignal is output each time the unit data string is generated.

(4) A serial-to-parallel conversion apparatus according to (3), whereinthe data string detection means (data storage device) includes: dataholding means for temporarily holding the serial data from one unit datastring to another in accordance with the clock signal; andsynchronization signal outputting means (synchronization signaloutputting device) for outputting the synchronization signal when theunit data string held by the data holding means has the predeterminedbit pattern.

In the apparatus according to (4), each unit data string is temporarilyheld by the data holding means, and the synchronization signal is outputwhen the unit data string held by the data holding means has the samepattern as the predetermined pattern set in advance in thesynchronization signal outputting means. This ensures that the seconddata string can be detected in a highly reliable fashion.

(5) A serial-to-parallel conversion apparatus according to (1), whereinthe signal generation means includes: data string detection means, towhich the clock signal and said serial data are input, for outputting anauxiliary synchronization signal each time a unit data string in thesecond data string is detected from the serial data; and synchronizationsignal outputting means for outputting the synchronization signal whendetecting a plurality of auxiliary synchronization signals output fromthe data string detection means.

In the apparatus according to (5), it is possible to generate anauxiliary synchronization signal each time a unit data string in thesecond data string is detected from the serial data. Because the unitdata string in the second data string is generated periodically, thesynchronization signal is output each time the unit data string isgenerated. This makes it possible to prevent an incorrect detection ofthe start point of the first data string when a single auxiliarysynchronization signal is generated erroneously.

(6) A serial-to-parallel conversion apparatus according to (5), whereinthe data string detection means includes: data holding means fortemporarily holding the serial data from one unit data string to anotherin accordance with the clock signal; and auxiliary synchronizationsignal outputting means (auxiliary synchronization signal outputtingdevice) for outputting the auxiliary synchronization signal when theunit data string held by the data holding means has the predeterminedbit pattern.

In the apparatus according to (6), each unit data string is temporarilyheld by the data holding means, and the auxiliary synchronization signalis output if the unit data string held by the data holding means has thesame pattern as the predetermined pattern set in advance in theauxiliary synchronization signal outputting means. This ensures that thesecond data string can be detected in a highly reliable fashion.

(7) A serial-to-parallel conversion apparatus according to (5) or (6),wherein the signal generation means further includes period controlsignal generation means (prior control signal generator) for generatinga period control signal whose voltage level is set to a predeterminedvalue over a second period entirely containing a first period, from itsbeginning to its end, in which a plurality of auxiliary synchronizationsignals are successively output, and wherein the auxiliarysynchronization outputting means outputs the auxiliary synchronizationsignal when the unit data string has the predetermined bit pattern.

In the apparatus according to (7), any auxiliary synchronization signalappears during the second period substantially corresponding to thesynchronization period. Therefore, unlike the apparatus according to(4), incorrect detection of the synchronization signal does not occureven if the bit pattern of unit data strings in the second data stringis not unique.

(8) A serial-to-parallel conversion apparatus according to (7), whereinthe detection signal generation means (first setting device) includes:first setting means for setting the start timing of the second period inaccordance with the auxiliary synchronization signal and the clocksignal; second setting means (second setting device) for setting the endtiming of the second period in accordance with the auxiliarysynchronization signal and the clock signal; and means for controllingthe voltage of the period control signal in accordance with the settingof the first and second setting means.

In the apparatus according to (8), the first setting means and secondsetting means set the start timing and end timing, respectively, of thesecond period by counting the clock signal generated after the auxiliarysynchronization signal is output, thereby generating the period controlsignal.

The present invention also provides a semiconductor device including aserial-to-parallel conversion apparatus according to one of (1) to (8),wherein the serial-to-parallel conversion apparatus is disposed on asemiconductor substrate.

The semiconductor device may be formed in the form of a single chip onwhich the serial-to-parallel conversion apparatus is formed, and may beinstalled in various types of information processing apparatus.

The present invention also provides an electronic device including: aserial-to-parallel conversion apparatus according to one of (1) to (8);and a display unit for displaying an image in accordance with paralleldata converted by the serial-to-parallel conversion apparatus.

In this electronic device, because the serial-to-parallel conversionapparatus based on one of (1) to (8) is employed, an image can bedisplayed on the displaying unit without encountering degradation inimage quality which may otherwise occur during data transmission.

The present invention also provides a data transmission system fortransferring data from a transmitting apparatus to a receivingapparatus, the transmitting apparatus comprising: an informationsupplying source for outputting a first clock signal and parallel data;means (second clock signal generator) for generating a second clocksignal by multiplying the first clock signal; and parallel-to-serialconversion means (parallel-to-serial conversion apparatus) for samplingthe parallel data in synchronization with the second clock signal andserially outputting data strings comprising unit data strings eachhaving a period corresponding to one cycle of the first clock signalsuch that a second data string including one or more unit data stringseach having a particular bit pattern for synchronization detection isserially output during a synchronization period and such that a firstdata string including one or more unit data strings is serially outputduring a period following the synchronization period, the receivingapparatus comprising: means for receiving the serial data (receivingdevice) and the second clock signal from the parallel-to-serialconversion means; signal generation means for detecting the second datastring in the serial data and generating a synchronization signalcorresponding to the synchronization period; serial-to-parallelconversion means (serial-to-parallel conversion apparatus) for detectingthe start position of the unit data string contained in the first datastring in the serial data on the basis of the synchronization signal andsampling the serial data in synchronization with the second clock signalthereby converting the serial data into parallel data from one unit datastring to another.

In this data transmission system, the serial-to-parallel conversionapparatus according to (1) is disposed as the receiving apparatus. Thus,the receiving apparatus in this system also has similar advantages tothose achieved by (1).

In this data transmission system, the transmitting apparatus preferablyincludes electric-to-optical signal conversion means(electric-to-optical signal converter) for converting the serial data inthe form of an electric signal to an optical signal, wherein theelectric-to-optical signal conversion means is preferably formed of asurface emitting laser.

Conventionally, semiconductor lasers of the edge emitting type arewidely used in communication systems and other applications. However,edge emitting lasers have a relatively large threshold current in therange from 20 to 50 mA, and thus a large bias current is required.Another problem of edge emitting lasers is that the threshold currentgreatly depends on temperature, and thus it is required to control thecurrent by way of feedback control (auto power control) while monitoringthe optical output so that the optical output is maintained constant.Therefore, a special type of driver is required to use an edge emittinglaser. This results in an increase in complexity of the system. Incontrast, the surface emitting laser employed in the preferable mode ofthe system has a small threshold current in the range from 0.05 mA to 10mA, and the temperature dependence of the threshold current can besuppressed to an extremely low level. Therefore, the surface emittinglaser can be driven using a simple modulation circuit. In the simplestcase which needs the lowest cost, an optical signal corresponding to anelectric signal can be generated by simply connecting the surfaceemitting laser to the parallel-to-serial conversion apparatus.

Furthermore, because the surface emitting laser operates in the singlelongitudinal mode, it has high monochromaticity and high stability interms of wavelength which allow it to be coupled with an optical fiberwith a high coupling efficiency. Another advantage of the surfaceemitting laser is that because it emits light in a directionperpendicular to the semiconductor substrate surface, the surfaceemitting laser can be mounted by means of chip bonding on an integratedcircuit chip such as a CMOS circuit into the form of a hybrid integratedcircuit. This form needs a single package and thus a reduction in costcan be achieved. Furthermore, optical signal transmission can beperformed at a high transmission rate which allows an increase inprocessing speed.

Furthermore, in the above data transmission system, theelectric-to-optical conversion means is preferably a multi-wavelengthsurface emitting laser.

In this preferable mode, it is possible to dispose light emitting partswhich emit light with different wavelengths at small intervals of theorder of 10 μm. Therefore, light rays with various wavelengths emittedfrom the multi-wavelength surface emitting laser can be coupled into atleast single optical transmission means with a relatively largediameter. This allows serial data and a multiplied clock signal or aplurality of serial data and a multiplied clock signal to be transmittedusing the single optical transmission means.

Furthermore, in the above data transmission system, it is desirable thata transmission medium for transmitting the clock signal and the serialdata be formed of a plurality of optical fibers, and theelectric-to-optical signal conversion means be formed of a multi-beamsurface emitting laser.

In this preferable mode, the multi-beam surface emitting laser includesthe plurality of light emitting parts which are arranged in aone-dimensional or two-dimensional fashion on a semiconductor substratechip, the light incidence ends of the plurality of optical fibers can beeasily positioned with respect to the array of light emitting partsthereby coupling the multi-beam surface emitting laser with theplurality of optical fibers. This makes it possible to achievetransmission via a plurality of optical fiber at low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrating the generalconfiguration of one embodiment of a data transmission system accordingto the present invention.

FIG. 2 is a block diagram illustrating the details of signal generationmeans of the system shown in FIG. 1.

FIG. 3 is a circuit diagram illustrating the details of the signalgeneration means shown in FIG. 1.

FIG. 4 is a block diagram illustrating a specific example of aserial-to-parallel converter shown in FIG. 1.

FIG. 5 is a block diagram illustrating another specific example of theserial-to-parallel converter shown in FIG. 1.

FIG. 6 is a timing chart illustrating an example of the operation of thesignal generation means configured as shown in the block diagram of FIG.2.

FIG. 7 is a timing chart illustrating an example of the operation of thecircuit shown in FIG. 3.

FIG. 8 is a timing chart illustrating an example of the operation of thecircuit shown in FIG. 3.

FIG. 9 is a timing chart illustrating an example of the operation of thesignal generation means configured as shown in the block diagram of FIG.2.

FIG. 10 is a timing chart illustrating an example of the operation ofthe signal generation means configured as shown in the block diagram ofFIG. 2.

FIG. 11(A) is a circuit diagram illustrating another example of thedetailed configuration of the signal generation means in the systemshown in FIG. 1, and FIG. 11(B) is a block diagram illustrating thedetails of the parallel-to-serial converter in the system shown in FIG.1.

FIG. 12 is a timing chart illustrating the operation of the circuitshown in FIG. 11.

FIG. 13 schematically illustrates examples of data strings in serialdata transmitted by the circuit shown in FIG. 12.

FIG. 14 is a functional block diagram illustrating the details of aliquid crystal display serving as an information processing apparatus inthe system shown in FIG. 1.

FIG. 15 is a block diagram illustrating another embodiment of aninformation transmission system according to the present invention.

FIG. 16 is a block diagram illustrating the general configuration of aconventional data transmission system.

FIGS. 17, 18, and 19 are timing charts illustrating the operation of thesystem shown in FIG. 16.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to drawings, a data transmission system, in which aserial-to-parallel conversion apparatus according to the presentinvention is employed, is described below in detail.

First Embodiment

(General System Configuration)

FIG. 1 illustrates the general configuration of one embodiment of a datatransmission system according to the present invention. In the datatransmission system 1 of the present embodiment, communication isperformed between one information processing apparatus 10 and anotherinformation processing apparatus 100 via transmission means(transmission device) 60.

In the present embodiment, one information processing apparatus 10serves to transmit data, and the other information processing apparatus100 serves to receive the data. A specific example of the oneinformation processing apparatus 10 is a personal computer (PC), andexamples of the other information processing apparatus 100 are a displaydevice including a liquid crystal display panel and a portable device.

The information processing apparatus 10 is connected to a transmittingapparatus 12 including, as shown in FIG. 1, a parallel-to-serialconverter 20, a phased-locked loop (PLL) 30, transmission drivers 40-1and 40-2, and an electric-to-optical signal conversion means(electric-to-optical signal converter) 50. On the other hand, theinformation processing apparatus 100 is connected to a receivingapparatus 108 including a serial-to-parallel converter 130, signalgeneration means (signal generator) 140, receivers 160-1 and 160-2, andan optical-to-electrical signal conversion means (optical-to electricsignal converter) 150. Herein, input means is formed by the receivers160-1 and 160-2 and the optical-to-electrical signal conversion means150.

The one information processing apparatus 10 outputs parallel data and adot clock signal-synchronized with the parallel data. The otherinformation processing apparatus 100 receives these signals and displaysan image in accordance with them.

Examples of data transmitted between the information processingapparatus 10 and 100 are a video synchronization signal (horizontalsynchronization signal H-sync, vertical synchronization signal V-sync),a video signal (R, G, B), and a clock signal. However, the presentinvention is not limited to these examples. The details, such as anarrangement, of data to be transmitted will be described later.

The parallel-to-serial converter 20 converts parallel data (R, G, B,H-sync, V-sync) output from the information processing apparatus 10 toone or more series of serial data. In the present embodiment, by way ofexample, 18-bit color video data is transmitted, wherein and thus theparallel-to-serial converter 20 has six input terminals for each of R,G, and B signals, one input terminal for each of the H-sync and V-syncsignals, and one output terminal. Thus, the parallel-to-serial converter20 has twenty terminals in total. However, the number of terminals isnot limited to this example. There may be provided a plurality of outputterminals as long as the number of output terminals is smaller than thenumber of input terminals.

A clock signal CL1 used in the above conversion process is supplied froma PLL 30 serving as a clock multiplier.

The PLL 30 generates the clock signal CL1 (multiplied clock signal)corresponding to the transmission rate of the serial data by multiplyingthe frequency of a dot clock signal CL0 (corresponding to thetransmission rate of image information) serving as a reference clocksignal. For example, when the frequency of the dot clock signal CL0 isequal to 25 MHz, this frequency is multiplied up to 500 MHz to generatethe clock signal CL1 used for synchronization associated with the 18-bitcolor video signal.

The frequency of the clock signal CL1 may be half the above frequency500 MHz, that is, 250 MHz, if the duty ratio thereof is 50% and if boththe rising and falling edges are used in the circuit operation. Althougha more complex circuit is required in this case, the reduction in theclock frequency allows circuit elements, interconnection lines, andtransmission lines to operate in a lower frequency band; which is moredesirable in practical applications. For simplicity, in the followingdiscussion, we assume that the clock frequency is equal to 500 MHz,unless otherwise noted.

The drivers 40-1 and 40-2 in the transmitting unit generates atransmission signal corresponding to the serial data output from theparallel-to-serial converter 20 and also generates a transmission signalcorresponding to the multiplied clock signal CL1 output from the PLL 30.

The resultant electric signals corresponding to the above data and theclock signal, respectively, are then converted to optical signals by theelectrical-to-optical signal conversion means 50 and transmitted via thetransmission means 60. The conversion into the optical transmissionsignals allows the signals to be protected from EMI and also allows themto be transmitted over a long distance. Furthermore, the receivingapparatus is not needed to perform frequency multiplication, and thus nojitter occurs in the receiving apparatus.

Preferably, the electrical-to-optical signal conversion means 50 isformed of a surface emitting laser, a multi-wavelength surface emittinglaser, or a multi-beam surface emitting laser. The transmission means 60serving as a transmission medium for transmitting the serial data ispreferably formed of one or more optical fibers (plastic fibers orplastic clad optical fibers). Preferably, the total length of thetransmission means 60 is about 100 m. Although in the presentembodiment, one transmitting apparatus and one receiving apparatus areconnected via one optical fiber serving as the transmission means 60,one transmitting apparatus and one receiving apparatus may also beconnected via a plurality of optical fibers whereby data may betransmitted.

The optical-to-electrical signal conversion means 150 in the receivingapparatus converts the optical transmission signals corresponding to thereceived serial data and clock signal, respectively, to electricalsignals. Preferably, the optical-to-electrical signal conversion means150 is formed of a GaAs PD or the like. Alternatively, a Si pinphotodiode or an InGaAs pin photodiode may be employed to form theoptical-to-electrical signal conversion means 150.

The transmission system constructed in the above-described manneroperates as follows. First, the horizontal synchronization signalH-sync, the vertical synchronization signal V-sync, and the RGB dataoutput from the information processing apparatus 10 are applied to theparallel-to-serial converter 20, and the clock signal CL0 output fromthe information processing apparatus 10 is applied to the PLL circuit30.

In accordance with the clock signal CL1 generated by the PLL circuit 30by means of frequency multiplication, the parallel-to-serial converter20 sequentially samples the parallel data (A0), . . . , (Ak) input via aplurality of, for example twenty, input lines thereby generating serialdata (A0 . . . Ak).

The resultant serial data is input to the electrical-to-optical signalconversion means 50 via the driver 40-1. The multiplied clock signal CL1output from the PLL 30 is also input to the electrical-to-optical signalconversion means 50 via the driver 40-2.

After being converted into optical signals by the electrical-to-opticalsignal conversion means 50, the serial data and the clock signal CL1 aretransmitted from the transmitting apparatus to the receiving apparatusvia the transmission means 60 formed of, for example, two opticalfibers.

If the receiving apparatus receives the optical signals of the serialdata and the clock signal via the transmission means 60, the opticalsignals are reconverted to electrical signals by theoptical-to-electrical signal conversion means 150 disposed in thereceiving apparatus.

The serial data output from the optical-to-electrical signal conversionmeans 150 is input as serial data DA1 to the serial-to-parallelconverter 130 and the signal generation means 140 via the receiver160-1.

On the other hand, the clock signal CL1 output from theoptical-to-electrical conversion means 150 is input to theserial-to-parallel converter 130 and the signal generation means 140 viathe receiver 160-2.

(Serial-to-Parallel Conversion Apparatus)

The serial-to-parallel conversion apparatus 120 is a part essential tothe present invention. As shown in FIG. 1, the serial-to-parallelconversion apparatus 120 is constructed in the form of a single-chipintegrated circuit including the serial-to-parallel converter 130, thesignal generation means 140, and the receivers 160-1 and 160-2 allformed on a semiconductor substrate.

The serial-to-parallel converter 130 serving as the data conversionmeans (data converter) converts serial data received via the receiver160-1 to parallel data (video synchronization signals (horizontalsynchronization signals H-sync, vertical synchronization signal V-sync),video signals (R, G, B)) in accordance with the multiplied clock signalCL1 generated by the transmitting apparatus and in accordance with thesecond auxiliary synchronization signal CL4. The resultant parallel datais sent to the information processing apparatus 100.

The serial-to-parallel converter 130 may be configured in variousmanners. Two preferable examples of the configuration are shown in FIGS.4 and 5, respectively.

In the example shown in FIG. 4, the serial-to-parallel converter 130includes: a shift register 131 serving as data holding means (storagedevice) for holding serial data (Rxin) in accordance with the clocksignal CL1; a counter 133 serving as counting means which operates inaccordance with the second auxiliary synchronization signal CL4 and theclock signal CL1; and a latch circuit 132 for outputting parallel data(Rxout0-Rxoutk) in accordance with the outputs of the counter 133 andthe shift register 131. In this configuration, the serial-to-parallelconverter 130 converts the sequentially-input serial data Rxin toparallel data in accordance with the timing specified by the output ofthe counter 133 and outputs the resultant parallel data Rxout0-Rxoutk.The second auxiliary synchronization signal CL4 resets the counter 133so that serial data is converted to parallel data at correct timingpoints.

In the example shown in FIG. 5, the serial-to-parallel converter 130includes: a demultiplexer 182 serving as data conversion means (dataconverter) for converting input serial data DA1 to parallel data; acounter 188 serving as counting means which operates in accordance withthe clock signal CL1 and a second auxiliary synchronization signal CL4which will be described later; a plurality of SR flip-flops 184 (184-1to 184-K) which are reset by the output of the counter 188 so as tocontrol the outputting of data from a plurality of output terminals ofthe demultiplexer 182; and a latch circuit 186 for latching andoutputting the outputs of the SR flip-flops 184 (184-1 to 184-K) inresponse to the output of the counter 188. Also in this configuration,sequentially-input serial data Rxin is converted to parallel dataRxout0-Rxoutk in accordance with the timing specified by the output ofthe counter 188. The second auxiliary synchronization signal CL4 resetsthe counter 188 so that serial data is converted to parallel data atcorrect timing points.

(Serial Data)

In the present invention, the term serial data is used to describe datacomprising a plurality of unit data strings each comprising a pluralityof serial bits. For example, each unit data string comprising bitsrepresenting one pixel of video signal and further one bit forhorizontal synchronization and another one bit for verticalsynchronization (a total of two bits for synchronization). Thus, in thecase where an 18-bit color image is displayed, each unit data stringcomprising 2 bits (for vertical and horizontal synchronization)+18 bits(representing R, G, and B intensity levels)=20 bits. In each 20-bit unitdata string, for example, most significant 2 bits are assigned to thevertical and horizontal synchronization, and the remaining lower-order18 bits are assigned to the R, G, and B intensity levels wherein 6 bitsof the lower-order 18 bits are used for each of the R, G, and Bintensity levels. In the case where a 24-bit color image is displayed,each unit data string comprising 2+24=26 bits. In this case, forexample, most significant 2 bits of each 26-bit unit data string areassigned to the vertical and horizontal synchronization, and theremaining lower-order bits are assigned to the R, G, and B intensitylevels wherein 8 bits are used for each of the R, G, and B intensitylevels.

More specifically, the number of pixels of one frame of image, thefrequency of the dot clock signal, and the video signal transmissionrate are given as shown in the following table.

Number of Pixels Dot Clock 18-Bit Color 24-Bit Color VGA 640 × 480 25MHz 500 Mbps 650 Mbps SVGA 800 × 600 40 MHz 800 Mbps 1.04 Gbps XGA 1024× 768  65 MHz 1.3 Gbps 1.69 Gbps SXGA 1280 × 1024 135 MHz 2.7 Gbps 3.51Gbps

That is, in the case of 18-bit color images, the transmission rate (inbps) becomes equal to 20 times the dot clock rate. On the other hand,the transmission rate for 24-bit color images, the transmission ratebecomes equal to 26 times the dot clock rate.

If the frequency of the dot clock signal CL0 is equal to, for example,25 MHz, the clock signal CL1 having a frequency of 500 MHz for the20-bit unit data string is produced by multiplying the frequency of thedot clock signal CL0 by a factor of 20.

In the following description, by way of example, 20-bit parallel datainput is serially transmitted from the transmitting apparatus 10 via thesingle transmission line 60, although the parallel data may also beserially transmitted via a plurality of transmission lines.

In the case where each unit data string is composed of 20 bits, theoperation is performed as follows. In FIGS. 6 and 9, serial data has avalue “00XXXX . . . XXXX” in each effective video period T8 wherein themost significant 2 bits are both “0” and the remaining lower-order 18bits XXXX . . . XXXX have values corresponding to the R, G, and Bintensity levels. One or more unit data strings are placed in eachperiod T8 shown in FIG. 9. Hereinafter, the data string comprising theone or more unit data strings in the period T8 is referred to as a firstdata string. On the other hand, in each video synchronization period T7shown in FIGS. 6 and 9, the most significant 2 bits of each unit datastring are both “1”, and the remaining lower-order bits are all “0”.That is, the unit data string in this period has a pattern “110000 . . .0000” which is used to detect a start position in the operation ofconverting the serial data into parallel form. Also in this period T7shown in FIG. 9, one or more unit data strings are placed, andhereinafter the data string comprising the one or more unit data stringsin this period is referred to as a second data string.

Herein, the video synchronization period T7 refers to either one of orboth of the vertical synchronization period and the horizontalsynchronization period. In the present invention, the signal indicatingthe start position is not necessarily needed in all vertical andhorizontal synchronization periods. For example, the signal indicatingthe start position may be placed only in the first one or moresynchronization periods of a plurality of frames which are successivelytransmitted. In this case, a unit data string indicating an ordinaryvertical or horizontal synchronization period is placed in any videosynchronization period T7 which is not used to detect the startposition. For example, a unit data string whose first bit is “1” and theremaining 19 bits are all “0” is used to indicate a verticalsynchronization period, and a unit data string whose second bit is “1”and the other 19 bits are all “0” is used to indicate a horizontalsynchronization period.

(Signal Generation Means)

The detailed configuration of the signal generation means 140 is nowdescribed below with reference to FIGS. 2 and 3.

As shown in FIG. 2, the signal generation means 140 includes data stringdetection means (data converter) 141 for outputting the first auxiliarysynchronization signal CL7; a flip-flop FF1 serving as synchronizationsignal outputting means for outputting the second auxiliarysynchronization signal CL4 in accordance with the first auxiliarysynchronization signal CL7; and period control signal generation means(period control signal generator) 144 for supplying a period controlsignal CL6 to the data string detection means 141.

The data string detection means 141 includes, as shown in FIG. 3, ashift register 142 serving as data holding means for temporarily holdingeach unit data string (comprising W bits (20 bits, for example)) of theserial data DA1 in response to the clock signal CL1.

The data string detection means 141 also includes a plurality ofinverters INV141 (142-1 to 142-K) for inverting the voltages of therespective bits of the unit data string output at the same time via klines from the shift register 142, except for the two highest-orderbits. That is, K (=W−2=18) bits are inverted by these inverters.

The data string detection means 141 further includes an AND gate AND1 towhich the two highest-order bits of the unit data string stored in theshift register 142 are input via output lines L1 and L2 and also theperiod control signal CL6 output from the period control signalgeneration means 144 and the outputs of the plurality of invertersINV142-1 to 142-K are input.

The flip-flop FF1 serving as the synchronization signal outputting means(synchronization signal outputting device) outputs the second auxiliarysynchronization signal CL4 in accordance with the first auxiliarysynchronization signal CL7 output from the AND gate AND1. In thisconfiguration, the flip-flop FF1 outputs the second auxiliarysynchronization signal CL4 only when the unit data string held in theshift register 142 has a predetermined pattern (11000 . . . 000) and theperiod control signal CL6 is “1”. In the present embodiment, theinverters INV142-1 to 142-K, the lines L1 and L2, and the AND gate AND1form auxiliary synchronization signal outputting means (auxiliarysynchronization signal outputting device).

The flip-flop FF1 serving as the synchronization signal outputting meansis disposed to remove glitches which area generated at boundaries ofdata by the shift register 142 and the AND gate AND1. Like the firstauxiliary synchronization signal CL7, the second auxiliarysynchronization signal is output one by one.

In the present embodiment, the flip-flop FF1 outputs the secondauxiliary synchronization signal CL4 in response to the first auxiliarysynchronization signal CL7. In the present embodiment, although not showin FIG. 3, there is preferably provided a counter for counting thesecond auxiliary synchronization signal CL4. The counter counts up thenumber of second auxiliary synchronization signals corresponding to asynchronization period T7 and outputs a synchronization signal used todetect the start position of the video signal.

In this case, the synchronization signal outputting means includes, inaddition to the flip-flop FF1, the counter (not shown) for counting thesecond auxiliary synchronization signals CL4 and means for outputtingone synchronization signal used to detect the start position of thevideo signal each time a plurality number of second synchronizationsignals CL4 are detected on the basis of the output of the counter.

This makes it possible to prevent a synchronization signal from beingerroneously output when a single first auxiliary synchronization signalis erroneously output, as will be described later.

When the period during which a plurality of first auxiliarysynchronization signals CL7 are successively output is referred to as afirst period (T7 in FIG. 7) and a period including the entire firstperiod from its beginning to its end is referred to as a second period(T1 in FIG. 7), the period control signal CL6 generated by the periodcontrol signal generation means 144 has a predetermined voltage levelover the second period T1.

The AND gate AND1 in the data string detection means 141 outputs thefirst auxiliary synchronization signal CL7 only when the period controlsignal CL6 is at a “1” level.

In the present embodiment, as described above, when in addition to thefirst condition associated with the predetermined pattern, the secondcondition that the period control signal CL6 is at the high level issatisfied, the first auxiliary synchronization signal CL7 becomes “1”,and, in response, the flip-flop FF1 outputs the second auxiliarysynchronization signal CL4. The first period T7 serves as a gatingsignal for outputting the second auxiliary synchronization signal CL4.Therefore, the method employed in the present embodiment is referred toas a detection-gating method.

In accordance with the clock signal CL1 and the first auxiliarysynchronization signal CL7, as shown in FIG. 3, the period controlsignal generation means 144 raises its output to the high level andmaintains it at that level over the predetermined period (T1) as isrepresented by the SR-FF output (video synchronization detection signal)in FIG. 7 thereby controlling the second auxiliary synchronizationsignal CL4 such that the second auxiliary synchronization signal CL4 isallowed to be output only during the period T1.

More specifically, the period control signal generation means 144includes: an inverter INV144 to which the output CL7 of the AND gateAND1 is input; a counter 145 serving as counting means which is reset bythe output of the inverter INV144 into a CLR (clear) state and whichperforms a counting operation in accordance with the clock signal CL1; acomparator 1 serving as first setting means (first setting device) whichoperates in accordance with the clock signal CL1 and the count value ofthe counter 145 such that an output signal 147-1 is output when thecount value reaches a preset value X1 (X11 EX12 E X13 E X14); acomparator 2 serving as second setting means (second setting device)which operates in accordance with the clock signal CL1 and the countvalue of the counter 145 such that an output signal 147-2 is output whenthe count value reaches a preset value X2 (X21 E X22 E X23 E X24); acomparator 3 serving as third setting means (third setting device) whichoperates in accordance with the clock signal CL1 and the count value ofthe counter 145 such that an output signal 147-3 is output when thecount value reaches a preset value X3 (X31 E X32 E X33 E X34); a NORgate NOR1 to which the output signal 147-1 of the comparator 1, theoutput signal 147-3 of the comparator 3, and the output of the inverterINV144 are input; and an SR flip-flop FF2 which is set by the output ofthe NOR gate NOR1 into a SET state and rest by the output signal 147-2of the comparator 2 into a RESET state and which outputs the periodcontrol signal CL6.

The comparator 1 serves to determine the start timing of the period T1shown in FIG. 7, and the comparator 2 serves to determine the end timingof the period T1 shown in FIG. 7. Thus, the preset value X1 associatedwith the comparator 1 is preferably set to a value equal to the countvalue corresponding to the periods T2+T3 shown in FIG. 7, and the presetvalue X22 associated with the comparator 2 is preferably set to a valueequal to the count value corresponding to the period T3 shown in FIG. 7.

On the other hand, the preset value X3 associated with the comparator 3is set to a value which causes the output voltage to become low when aperiod equal to T3+T2+T1 shown in FIG. 7 has elapsed after the counter145 started the counting operation.

More specifically, if the count value of the counter 145 reaches thepreset value X3, the output signal 147-3 of the comparator falls down tothe low level. The counter 145 performs a counting operation when itsenable input EN is at a high level. The counter 145 stops the countingoperation when the enable input EN becomes low and holds the countvalue. When the counter 145 holds the count value at X3, the outputsignal 147-3 falls down to the low level, and the period control signalCL6 is maintained at the high level.

Herein, if the synchronization pattern is detected in the serial data,the counter is reset by the inverter INV44, and the counter restarts thecounting operation.

In order to control the operation more precisely, N comparators servingas setting means for setting the period may be connected to the counter145 via output lines Xn.

(Operations of the Signal Generation Means, Data String Detection Means,and Synchronization Signal Outputting Means)

The operations of the serial-to-parallel conversion apparatus and thesignal generation means in the data processing system are describedbelow with reference to FIGS. 1, 3, 7, and 8.

The clock signal CL1 output from the optical-to-electrical signalconversion means 150 is input to the serial-to-parallel converter 103via the receiver 160-2. The clock signal CL1 is also input to the signalgeneration means 140.

In accordance with the clock signals CL4 and CL1 supplied from thesignal generation means 140, the serial-to-parallel converter 130converts the serial data DA1 to parallel data R, G, B, H-sync, andV-sync and outputs the resultant data.

The output data R, G, B, H-sync, and V-sync are input to the informationprocessing apparatus 100 disposed at the transmitting end. The clocksignal CL5 output from the signal generation means 140 is also input tothe information processing apparatus 100.

Now, the operation of the signal generation means 140 is describedbelow. The serial data DA1 and the clock signal CL1 are input to thesignal generation means 140. As shown in FIG. 3, the serial data DA1 isfirst input to the shift register 142 of the data string detection means141 disposed in the signal generation means 140.

The shift register 142 holds the serial data from one unit data string(comprising, for example, 20 bits) to another. The lower-order 18 bitsof the output signal of the shift register 142 are applied to inputterminals of the AND gate AND1 via the inverters INV142-1, . . . ,INV142-K, respectively, and the most significant 2bits are applied toinput terminals of the AND gate AND1 via lines L1 and L2.

Thus, only when the output signal of the shift register 142 has apattern 11000 . . . 000 (20 bits) and the period control signal CL6 isat the high level, the signal level at the output terminal of the ANDgate AND1 becomes high.

The output signal of the AND gate AND1 is applied to the D-inputterminal of the flip-flop FF1 and also to the inverter INV144.

In response, the flip-flop FF1 outputs the second auxiliarysynchronization signal CL4 via the Q output terminal. That is, thesecond auxiliary synchronization signal CL4 with the high level isoutput only when the period control signal CL6 is at the high level andthe unit data string has the pattern 11000 . . . 000 (20 bits).

The most significant 2 bits of the unit data string are used to indicatethat the unit data string is a video synchronization signal (verticalsynchronization signal H-sync or vertical synchronization signalV-sync), and the lower-order 18 bits indicate intensity levels (R, G,and B) of the video signal.

Therefore, when the most significant 2 bits are at the high level (thatis, when the video synchronization signal is enabled), the lower-order18 bits are meaningless. In this case, therefore, the lower-order 18bits of each unit data string of the second data string in the videosynchronization period T7 shown in FIG. 6 are all set to the low levelso that the unit data string has the predetermined bit pattern. However,there is a possibility that, during the period T8 shown in FIG. 6 inwhich the video synchronization signal is disabled, some unit datastring can have a pattern comprising 18 low-level bits following firsttwo high-level bits.

To avoid a problem, the period control signal CL6 is raised to the highlevel only during the period T1 containing the period T7 during whichthe video synchronization signal is enabled (at the high level) therebyassuring that the second auxiliary synchronization signal CL4 is outputfrom the signal generation means 140 only during the period T1.

That is, the period control signal CL6 output from the SR flip-flop FF2is raised to the high level immediately before the video synchronizationsignal rises to the high level and maintained at that level until thevideo synchronization signal has fallen down to the low level (that is,during the period T1 shown in FIG. 7) thereby assuring that the outputof the AND gate AND1 shown in FIG. 3 becomes high only when the periodcontrol signal CL6 is high and thus the second auxiliary synchronizationsignal CL4 is output only when during this period.

During the period T7 in which the video synchronization signal is at thehigh level, a unit data string having a pattern “11000 . . . 00” (20bits) appears in the serial data at a plurality of times (six times inthe example shown in FIG. 6) at intervals of T11. In this case, if theflip-flop FF1 and other circuit elements are configured as in FIG. 3,the second auxiliary synchronization signal CL4 is output after a delayof T12 (one clock cycle) shown in FIGS. 6 and 7 with respect to thefirst bit of the unit data string “11000 . . . 00” (20 bits) appearingfirst in the second data string during the period T7.

As a result, the first auxiliary synchronization signal CL7corresponding to each unit data string “11000 . . . 00” (20 bits) in theperiod T7 is output after a delay of T12 with respect to the beginningof the period T7. However, because first auxiliary synchronizationsignals are output at intervals of T11 which are equal to intervals atwhich unit data strings “11000 . . . 00” (20 bits) are output, the starttiming of the video signal period T8 is precisely reflected in therising-up timing of the second auxiliary synchronization signal CL4.

As described above, unit data strings “11000 . . . 00” (20bits) withinthe period T7 are detected from the serial data, and the secondauxiliary synchronization signal CL4 is output in response of detectionof the unit data strings. Thus, in the operation in which theserial-to-parallel converter 130 converts serial data comprising aplurality of unit data strings to parallel data, the position of thefirst bit of the video signal in the period T8 is detected on the basisof the output of the second auxiliary synchronization signal CL4, andthe detected first bit of the video signal is output via, for example,the terminal RXout1. Thus, the serial data is correctly converted toparallel data.

At a time when a predetermined number of second auxiliarysynchronization signals CL4, which are generated at intervals of T11,have been detected, serial-to-parallel conversion is performed.

In the present embodiment, unit data strings “11000 . . . 00” (20 bits)used to indicate the start position can be generated in the transmittingapparatus 12, because the horizontal synchronization signal H-sync andthe vertical synchronization signal V-sync are input to theparallel-to-serial converter 20 in the transmitting apparatus 12 shownin FIG. 1.

(Operation of Generating the Period Control Signal)

The operation of generating the period control signal CL6 is describedbelow.

First, a first auxiliary synchronization signal CL7 output from the ANDgate AND1 via its output terminal and a clock signal CL1 are input tothe period signal generation means 144.

The first auxiliary synchronization signal CL7 is applied to theinverter INV144, and the output signal of the inverter INV144 is appliedto the CLR terminal of the counter 145. Therefore, when the firstauxiliary synchronization signal CL7 is at the high level, the counter145 is cleared, as can be seen from the timing chart shown in FIG. 7. InFIG. 7, the counter 145 is cleared each time the first auxiliarysynchronization signal CL7 rises to the high level.

After being cleared, the counter 145 counts the clock signal CL1. If thecount value of the counter 145 reaches a predetermined valuecorresponding to a period of T3 shown in FIG. 7, the output of thecomparator-2 (146-2) falls down to the low level.

The output signal of the comparator-2 (146-2) is applied to the RESETinput terminal of the SR flip-flop FF2, and thus the period controlsignal CL6 output from the SR flip-flop FF2 falls down to the low levelas shown in FIG. 7. The falling-down of the period control signal CL6defines the end of the second period T1 shown in FIG. 7.

The counter 145 further counts the clock signal CL1. When the countvalue reaches a value corresponding to the period (T3+T2) shown in FIG.7, the output of the comparator-1 (146-1) falls down to the low level.As a result, the SR flip-flop FF2 is set into a SET state via the NORgate NOR1, and thus the period control signal CL6 output from the SRflip-flop FF2 rises to the high level. The rising-up of the periodcontrol signal CL6 defines the start of the second period T1 shown inFIG. 7.

Thereafter, the above operation is performed repeatedly. Thus, as shownin FIG. 7, the period control signal CL6 output from the SR flip-flopFF2 becomes high during each second period T1 containing the entirelength of a first period T7, from its beginning and to its end, duringwhich the video synchronization signal is enabled.

As described above, the period control signal CL6 is made high over eachperiod T1 by the comparator-1 (146-1) and the comparator-2 (146-2).

There is a chance, as shown in FIG. 8, that a certain unit data stringof the video signal has a pattern same as the predetermined pattern11000 . . . 000 (20 bits) after the output of the comparator-1 becamelow. In this case, the counter 145 is reset (cleared), and the output ofthe comparator-2 becomes low when a period of T3 has elapsed since thecounter 145 was reset. As a result, the period control signal CL6becomes high during a period other than the period T7, and a unit datastring having the predetermined pattern 11000 . . . 000 (20 bits) isdetected during that period other than the period T7. Thus, a firstauxiliary synchronization signal CL7 is output from the AND gate AND1.However, the possibility is extremely low that the pattern (11000 . . .000) appears in successive unit data strings, and thus there issubstantially no possibility that two or more first auxiliarysynchronization signals CL7 are successively output. Therefore, when thecount value of the counter 145 reaches a value corresponding to theperiod T3, the output of the comparator-2 (146-2) becomes low as shownin FIG. 8. Thus, the period control signal CL6 (output from the SRflip-flop FF2 ) soon returns to the low level.

Then, after T3+T2, the output of the comparator-1 (1461-) becomes low.

If the count value of the counter 145 reaches a predetermined value(corresponding to T3+T2+T4 shown in FIG. 8), the output of thecomparator-3 (146-3) becomes high (the signal line 147-3 becomes low).As a result, the comparator-3, instead of the comparator-1, sets the SRflip-flop FF2 via the NOR gate NOR1 thereby raising the period controlsignal CL6 to the high level. If the count value of the counter 145reaches a preset value X3 and the output of the comparator-3 becomeslow, the enable input EN of the counter 145 becomes low, and thus thecounter 145 stops its operation and the count value of the counter 145is maintained at X3. As a result, the period control signal CL6 isfurther maintained at the high level over the following period T5 shownin FIG. 8. After the period T5, unit data strings 11000 . . . 000 (20bits) serving as correct signals indicating the start position aredetected, and the start position detecting operation restarts in anormal manner.

(Electric-to-Optical Conversion Means)

The details of the electric-to-optical conversion means 50 are describedbelow. In FIG. 1, the electric-to-optical signal conversion means 50 inthe transmitting apparatus is formed of, for example, a surface emittinglaser, and more preferably, a multi-wavelength surface emitting laser ora multi-beam surface emitting laser.

Conventionally, semiconductor lasers of the edge emitting type arewidely used in communication systems and other applications. However,edge emitting lasers have a relatively large threshold current in therange from 20 to 50 mA, and it is required that a large bias current besupplied. Another problem of edge emitting lasers is that the thresholdcurrent greatly depends on temperature, and thus it is required tocontrol the current by means of feedback control (auto power control)while monitoring the optical output so that the optical output ismaintained constant. Therefore, a special type of driver is required touse an edge emitting laser. This results in an increase in complexity ofthe system.

In contrast, the surface emitting laser employed in the presentembodiment has a small threshold current in the range from 0.05 mA to 10mA, and the temperature dependence of the threshold current can besuppressed to an extremely low level. Therefore, the surface emittinglaser can be driven using a simple modulation circuit. Thus, use of thesurface emitting laser allows a reduction in the cost of the laserdriver.

In the simplest case which needs the lowest cost, an optical signalcorresponding to an electric signal can be generated by simplyconnecting the surface emitting laser to the output of a CMOS circuitforming the parallel-to-serial converter. Furthermore, because thesurface emitting laser operates in the single longitudinal mode, it hashigh monochromaticity and high stability in wavelength which allow it tobe coupled with an optical fiber with a high coupling efficiency.

Another advantage of the surface emitting laser is that because it emitslight in a direction perpendicular to the semiconductor substratesurface, the surface emitting laser can be mounted by means of chipbonding on an integrated circuit chip such as a CMOS circuit into theform of a hybrid integrated circuit. This form needs a single packageand thus a reduction in cost can be achieved.

If a multi-wavelength surface emitting laser is used, it is possible todispose light emitting parts which emit light with different wavelengthsat small intervals of the order of 10 μm. Therefore, by coupling themulti-wavelength surface emitting laser with an optical fiber with alarge diameter (100 μm or greater), it becomes possible to transmitlight rays with various wavelengths emitted from the multi-wavelengthsurface emitting laser via the single optical fiber. This allows serialdata and a multiplied clock signal or a plurality of serial data and amultiplied clock signal to be transmitted using the single opticalfiber.

On the other hand, a multi-beam surface emitting laser has across-sectional structure having a plurality of light emitting points(light emitting parts) on a single semiconductor substrate. Thisstructure provides an advantage in terms of layout in that the pluralityof light emitting points can be easily positioned with respect to thelight incidence end of an optical fiber.

In the case where a plurality of optical fibers bound in the form of aribbon or a honey comb are employed, the light emitting points of themulti-beam surface emitting laser may be formed at locationscorresponding to the array of optical fibers, thereby making it possibleto achieve high positioning accuracy, and also making it possible toachieve a multi-fiber transmission system at low cost. This techniquealso makes it easy to produce the surface emitting laser.

In the first embodiment, as described above, the first bit can beidentified by detecting the above pattern in the serial-to-parallelconversion. Therefore, it becomes possible to perform serial-to-parallelconversion without requiring the clock signal to include informationindicating the first bit. In this technique, the multiplied clock signalCL1 is transmitted, instead of the dot clock signal CL0.

In the case where image information is transmitted to a CRT or a similardevice, it is not required that the number of RGB elements of the CRT bejust equal to the number of pixels of the image information. Therefore,in this case, no significant degradation occurs in image quality even ifthe image information is transmitted using an analog transmissiontechnique. In contrast, in the liquid crystal display panel, it isrequired that the number of RGB elements should be precisely equal tothe number of pixels of the image information. If there is a difference,significant degradation in image quality occurs. In this regard, in thepresent embodiment, serial-to-parallel conversion can be performedprecisely and thus an image can be displayed on the liquid crystaldisplay panel without encountering degradation in image quality.Furthermore, because no PLL is required in the receiving apparatus, areduction in cost can be achieved.

Although the multiplied clock signal CL1 has a relatively highfrequency, the multiplied clock signal CL1 as well as the imageinformation can be transmitted in the form of an optical signal withoutencountering significant electromagnetic interference (EMI) which is aproblem in conventional transmission techniques using electric signals.

In conventional analog transmission systems, the maximum possibletransmission distance is limited to a rather small range. In contrast,the combination of digital transmission and optical transmissionaccording to the present embodiment allows long distance transmission.However, the digital transmission needs an extremely high transmissioncapacity. The optical transmission allows increases in transmissioncapacity and the maximum allowable transmission distance and reductionsin the diameter of the cable and the power consumption.

Use of the multi-wavelength surface emitting laser makes it possible toreduce the frequency band without increasing the number of fibers. Ifthe frequency band is fixed, the multi-wavelength surface emitting laserallows a greater amount of data to be transmitted, and thus it becomespossible to drive a large-sized high-resolution display. Furthermore,use of the multi-beam surface emitting laser makes it possible toincrease the transmission capacity without resulting in an increase inthe cost of the surface emitting laser.

In the present embodiment, as descried above with reference to FIG. 1,the serial-to-parallel conversion apparatus 120 includes theserial-to-parallel converter 130, the signal generation means 140, andthe receivers 60-1 and 60-2, which are all formed on a signal chip. Inthis case, a circuit such as a preamplifier (transimpedance amplifier)for the pin photodiode is disposed in the optical-to-electric conversionmeans 150.

In the transmitting apparatus, the parallel-to-serial converter 20, thePLL 30, the drivers 40-1 and 40-2 are constructed on a single chip. Notethat these elements including the drivers 40-1 and 40-2 can beconstructed on the single chip only when a surface emitting laser isemployed and the drivers are constructed using a CMOS circuit or thelike.

Furthermore, in the present embodiment, as described above withreference to the timing chart of FIG. 9, blank periods (T9) are disposedin serial data such that each blank period is placed between each videosynchronization data string and the following video data string.However, blank periods T9 are not necessarily required, and videosynchronization data strings and video data strings may be placed asshown in the timing chart of FIG. 10. However, in order to obtain asufficient margin for switching timing, it is desirable to dispose blankperiods.

Second Embodiment

A second embodiment of the present invention is now described below.FIGS. 11(A) and 11(B) illustrate an example of a serial-to-parallelconversion apparatus using an overhead bit technique in addition to thedetection-gating technique described above. In the following discussion,similar parts to those in the first embodiment are not described.

In the serial-to-parallel conversion apparatus of the presentembodiment, as shown in FIG. 11(A), the signal generation means isformed of only a synchronization signal generator 200. Thissynchronization signal generator 200 is different from thesynchronization signal generator employed in the first embodiment inthat a synchronization signal CL4 is output only when a unit data stringhaving a unique pattern indicating the start position, which neverappears in image intensity level data, is detected in serial data.

In the first embodiment, in the case of an 18-bit color video signal, 2bits for vertical and horizontal synchronization are added to form eachunit data sting. Thus, in the first embodiment, each unit data stringcomprising 20 bits in total. In the present embodiment, one overhead bitis further added, and thus each unit data string is composed of 21 bitsin total. Herein, the most significant bit is used for verticalsynchronization (which becomes high during each vertical synchronizationperiod), and the second bit is used as the overhead bit (always at thehigh level). The third bit is used for horizontal synchronization (whichbecomes high during each horizontal synchronization period), and theremaining 18 bits are used to represent image intensity level, wherein 6bits are used for each of R, G, and B levels. Herein, a pattern “111000. . . 000” (21 bits) is employed as a unique pattern used to indicatethe start position, and unit data strings in each image display periodare given in the form of “010XXX . . . XXX” (21 bits).

The synchronization signal generator 200 for generating such datastrings may be configured as follows.

That is, as shown in FIG. 11(A), output terminals of a shift register202 are coupled with input terminals of an AND gate AND 200 such thatthe most significant 3 bits of the outputs are directly connected vialines L1, L2, and L3 (L1, . . . , Lm where m=3) and the remaining 18bits are connected via 18 inverters INV203-1 to 203-k (k=W−3=21−3=18).

Thus, in the synchronization signal generator 200, data string detectionmeans for detecting a unit data string having the unique pattern isformed of the inverters INV203-1 to 203-k, the lines L1, L2, and L3, theAND gate AND200, and the shift register 202. There is also provided aflip-flop FF200 having a similar function to that of the flip flop FF1in the first embodiment.

In order to generate unit data strings having the unique pattern “111000. . . 000” (21 bits), a parallel-to-serial converter 210 serving as datastring generation means for generating a data string having the uniquepattern in serial data is disposed in a transmitting apparatus as shownin FIG. 11(B).

This parallel-to-serial converter 210, unlike the serial-to-parallelconverter in the first embodiment described above, an input terminalcorresponding to the second most significant bit is connected to VDD(high-level voltage), and input terminals Txin0-Txink corresponding tothe remaining bits are used as normal input terminals.

That is, a data string having the unique pattern “111000 . . . 000” (Wbits) can be generated by connecting the input terminal corresponding tothe second most significant bit, which should be always “1”, to VDD, andthe remaining k (k=21−1=20) input terminals Txin0-Txink are used asnormal input terminals. A vertical synchronization signal H-sync isinput to an input terminal Txin0 corresponding to the most significantbit, and a horizontal synchronization signal V-sync is input to an inputterminal Txin1 corresponding to the third most significant bit. R, G,and B signals are input to the remaining bits.

Thus, a 21-bit unit data string whose second bit is always set to “1” asthe overhead bit is serially output.

When an image signal is transmitted, patterns become, for example, asshown at the top of FIG. 13. On the other hand, when the videosynchronization signal is enabled, patterns become, for example, asshown at the bottom of FIG. 13. As can be seen from FIG. 13, a bitpattern having 3 successive “1”s followed by 18 “0”s, that is,“111000000000000000000” never appears in periods during which an imagesignal is transmitted. In other words, even if 3 successive “1” appearin image intensity level signals, an overhead bit “1” appears within thefollowing 18 bits. Thus, the unique pattern is detected only when thevideo synchronization signal is enabled as shown in FIG. 12. Therefore,the output CL4 of the flip-flop FF200 can be used as a synchronizationsignal indicating the start of the video signal. Furthermore, unlike thefirst embodiment, it is not required to gate the second period T1 shownin FIG. 7 using a circuit including a counter, a comparator, and a flipflop. Therefore, the circuit configuration becomes simpler.

The unique pattern is not limited to the specific example describedabove. Any unit data string pattern may be employed as long as it neverappears in video signals. For example, in stead of using one overheadbit, N (N=1) overhead bits may be used.

Third Embodiment

An embodiment of an electronic device using the above-describedinformation processing apparatus is described below with reference toFIG. 14.

The electronic device of the present embodiment includes theserial-to-parallel conversion apparatus 120 described above and aninformation processing apparatus 100 connected to thisserial-to-parallel conversion apparatus 120.

The information processing apparatus 100 may have an internal structuresuch as that shown in FIG. 14. That is, the information processingapparatus 100 includes: a frame memory writing circuit 102 whichreceives video signals R, G, and B, a horizontal synchronization signalHSYNC, and a vertical synchronization signal VSYNC from theserial-to-parallel conversion apparatus 120; a frame memory 106 forstoring a video signal as data D1; a frame memory reading circuit and aliquid crystal display controller 103 for reading the video signal fromthe frame memory 106 and outputting it as display data D2; a liquidcrystal display panel 104 for displaying an image; and a video processor101 connected to the frame memory 106, for performing processes such asinterpolation, error correction, and decompression upon the video data.

There is also provided a write address converter 105 for performing, inaccordance with the clock control signal CL5, write address conversionand supplying the resultant address to the frame memory 106.

In this apparatus, the frame memory writing circuit 102 generates awriting address SWA and supplies it to the writing address converter 105in accordance with the horizontal synchronization signal HSYNC and thevertical synchronization signal VSYNC supplied from theserial-to-parallel conversion apparatus 120.

The frame memory writing circuit 102 synchronizes the video signals R,G, and B to the vertical synchronization signal VSYNC and sends thewrite data D1 and a write/read switching signal SRD to the frame memory106 in synchronization with the horizontal synchronization signal HSYNC.The write address converter 105 converts the write address SWA to anarbitrary address and sends it to the frame memory 106. Upon receivingthe signal SRD, the frame memory 106 goes into a write mode and writesthe write data D1 at a specified address.

In synchronization with the signals HSYNC and VSYNC, the frame memoryreading circuit and liquid crystal display controller 103 reads datafrom the frame memory 106 in the same order as is written, and suppliesit together with a liquid crystal control signal to the liquid crystaldisplay panel 104.

The liquid crystal display panel 104 includes a liquid crystal displaydriver. In response to the liquid crystal control signal, the liquidcrystal display driver displays an image in synchronization with thehorizontal synchronization signal HSYNC which is given a predeterminednumber of times during each frame period.

One frame of video synchronization signals R, G, and G are written intothe frame memory 106 in synchronization with the verticalsynchronization signal VSYNC and the horizontal synchronization signalHSYNC. The video signals written in the frame memory 106 are then readin synchronization with the vertical synchronization signal VSYNC andthe horizontal synchronization signal HSYNC and displayed insynchronization with a predetermined number of horizontalsynchronization signals.

The liquid crystal display panel 104 includes driving means and adisplay panel constructed in the form of an LCD module. The drivingmeans includes a signal line driver, a scanning line driver, and a powersupply circuit.

The electronic device described above may include a display informationoutput source. In this case, the display information output source mayinclude a memory such as a ROM or a RAM and a tuning circuit foroutputting a tuned television signal. The liquid crystal displaycontroller may include an amplification/inversion circuit, a phaseexpansion circuit, a rotation circuit, a gamma correction circuit,and/or clamping circuit.

Specific examples of the electronic device are a liquid crystalprojector, a multimedia personal computer (PC), a multimedia engineeringwork station (EWS), a word processor, a television set, a video taperecorder with a viewfinder or a monitor, a computer, a POS terminal, andan apparatus provided with a touch panel.

Fourth Embodiment

FIG. 15 illustrates an example in which the data transmission systemdescribed above is used together with a personal computer and a liquidcrystal display of widely-used types.

In FIG. 15, a PC 300 is used as one information processing apparatus,and a liquid crystal display 400 is used as the other informationprocessing apparatus. A serializer 320 is used as the serial-to-parallelconverter, and a deserializer 430 is used as the parallel-to-serialconverter. The transmission medium is formed of a plurality of opticalfibers 350 serving as a plurality of transmission lines for transmittingserial data.

The serializer 320 has a plurality of output terminals and thedeserializer 430 has a plurality of input terminals so that a pluralityof serial data can be transmitted in parallel depending on the amount ofdata. There may be provided a plurality of transmission lines fortransmitting clock signals, as required.

Although the present invention has been described above with referenceto specific embodiments of apparatus and methods, those skilled in theart will appreciate that various modifications can be made withoutdeparting from the spirit and scope of the present invention. Forexample, although in the embodiments described above, 110000 . . . 000is employed as the unique data string pattern, the present invention isnot limited to such a pattern. What is essential is that the data stringhas a unique pattern which never appears in the video signal. Thus, anypattern such as “000011100001”, “0000 . . . 00001111”, or “0000 . . .0001111” may be employed as long as it is unique. A data string havingsuch a unique pattern may be produced by configuring theparallel-to-serial converter serving as the unique pattern generator inthe transmitting apparatus such that a particular pin corresponding to abit which should be “1” is set to a high level, and by configuring thesynchronization signal generator in the signal generation means suchthat the outputs of the shift register 142 and the inputs of the ANDgate AND1 are connected in a manner corresponding to the unique pattern.

For example, in the case where “0000 . . . 0000111” is employed as theunique pattern, the VCC voltage is supplied to three lowest-order inputterminals of the parallel-to-serial converter 20, and thesynchronization signal generator is configured such that the leftmostthree outputs are directly connected via lines L1, L2, and L3, and theremaining outputs are connected via inverters.

Furthermore, although a LCD display is employed as the display in theembodiments described above, the invention is not limited to the LCDdisplay. For example, a small-sized television set using a thin-shapedCRT or a liquid crystal shutter, a plasma display, or anelectroluminescence display may also be employed.

A system may include two liquid crystal displays each includingtransmitting and receiving apparatus using a serial-to-parallelconversion apparatus according to the invention thereby allowing two-waycommunication.

What is claimed is:
 1. A serial-to-parallel conversion apparatus,comprising: a data converter that samples serial data comprising a firstdata string that includes one or more unit data strings, each datastring including a predetermined number of bits, the serial data beinginput after a synchronization period in accordance with a clock signalwhich has been used to generate the serial data by converting originalparallel data into serial form from one unit data string to another; anda signal generator that generates a synchronization signal correspondingto the synchronization period, on the basis of the serial data, theserial data including a second data string for synchronization detectionwithin the synchronization period, the second data string including oneor more unit data strings each having a predetermined bit pattern, thesignal generator generating the synchronization signal when detectingthe unit data string in the second data string, and the data converterdetecting the start position of the unit data string in the first datastring based on the synchronization signal.
 2. The serial-to-parallelconversion apparatus according to claim 1, the bit pattern of the unitdata string in the second data string being a unique pattern differentfrom any bit pattern in the unit data string in the first data string.3. The serial-to-parallel conversion apparatus according to claim 2, thesignal generator including a data string detector to which the clocksignal and the serial data are input, that detects the unit data stringin the second data string from the serial data thereby outputting thesynchronization signal.
 4. The serial-to-parallel conversion apparatusaccording to claim 3, the data string detector including a data storingdevice that temporarily stores the serial data from one unit data stringto another in accordance with the clock signal, and a synchronizationsignal output device that outputs the synchronization signal when theunit data string stored by the data storage device has the predeterminedbit pattern.
 5. The serial-to-parallel conversion apparatus according toclaim 1, the signal generator including a data string detector to whichthe clock signal and the serial data are input, that outputs anauxiliary synchronization signal each time the unit data string in thesecond data string is detected from the serial data, and asynchronization signal output device that outputs the synchronizationsignal when a plurality of the auxiliary synchronization signals outputfrom the data string detector are detected.
 6. The serial-to-parallelconversion apparatus according to claim 5, the data string detectorincluding a data storage device that temporarily stores the serial datafrom one unit data string to another in accordance with the clocksignal, and an auxiliary synchronization signal output device thatoutputs the auxiliary synchronization signal when the unit data stringheld by the data storage device has the predetermined bit pattern. 7.The serial-to-parallel conversion apparatus according to claim 5, thesignal generator further including a period control signal generatorthat generating a period control signal whose voltage level is set to apredetermined value over a second period entirely containing a firstperiod, from its beginning to its end, in which a plurality of auxiliarysynchronization signals are successively output, and the synchronizationoutput device outputting the auxiliary synchronization signal when theunit data string has the predetermined bit pattern.
 8. Theserial-to-parallel conversion apparatus according to claim 5, the signalgenerator further including a period control signal generator thatgenerating a period control signal whose voltage level is set to apredetermined value over a second period entirely containing a firstperiod, from its beginning to its end, in which a plurality of auxiliarysynchronization signals are successively output, and the auxiliarysynchronization output device outputting the auxiliary synchronizationsignal when the unit data string has the predetermined bit pattern. 9.The serial-to-parallel conversion apparatus according to claim 7, thedetection signal generator including a first setting device that setsthe start timing of the second period in accordance with the auxiliarysynchronization signal and the clock signal, a second setting devicethat sets the end timing of the second period in accordance with theauxiliary synchronization signal and the clock signal, and a controllerthat controls the voltage of the period control signal in accordancewith the setting of the first and second setting device.
 10. Theserial-to-parallel conversion apparatus according to claim 8, thedetection signal generator including a first setting device that setsthe start timing of the second period in accordance with the auxiliarysynchronization signal and the clock signal, a second setting devicethat sets the end timing of the second period in accordance with theauxiliary synchronization signal and the clock signal, and a controllerthat controls the voltage of the period control signal in accordancewith the setting of the first and second setting device.
 11. Thesemiconductor device, comprising: the serial-to-parallel conversionapparatus according claim 1, the serial-to-parallel conversion apparatusbeing disposed on a semiconductor substrate.
 12. An electronic device,comprising: the serial-to-parallel conversion apparatus according toclaim 1; and a display unit that displays an image in accordance withparallel data converted bay the serial-to-parallel conversion apparatus.13. The serial-to-parallel conversion apparatus according to claim 1,the second data string including one or more unit data strings eachcomprising a plurality of bits having a predetermined bit pattern. 14.The serial-to-parallel conversion apparatus according to claim 1, thedata converter detecting the start position of the unit data string inthe first data string based on the synchronization signal withoutvariably delaying the first data string.
 15. A data transmission systemfor transferring data from a transmitting apparatus to a receivingapparatus, the transmitting apparatus comprising: an informationsupplying source that outputs a first clock signal and parallel data; asecond clock signal generator that generates a second clock signal bymultiplying the first clock signal; and a parallel-to-serial conversionapparatus that samples the parallel data in synchronization with thesecond clock signal and serially outputs data strings comprising unitdata strings each having a period corresponding to one cycle of thefirst clock signal such that a second data string including one or moreunit data strings each having a particular bit pattern forsynchronization detection is serially output during a synchronizationperiod and such that a first data string including one or more unit datastrings is serially output during a period following the synchronizationperiod; the receiving apparatus comprising: a receiving device thatreceives the serial data and the second clock signal from theparallel-to-serial conversion apparatus; a signal generator that detectsthe second data string in the serial data and generates asynchronization signal corresponding to the synchronization period; anda serial-to-parallel conversion apparatus that detects the startposition of the unit data string contained in the first data string inthe serial data based on the synchronization signal and samples theserial data in synchronization with the second clock signal to convertthe serial data into parallel data from one unit data string to another.16. The data transmission system according to claim 15, the transmittingapparatus including an electric-to-optical signal converter thatconverts the serial data in the form of an electric signal to an opticalsignal.
 17. The data transmission system according to claim 16, theelectric-to-optical signal converter including a surface emitting laser.18. The data transmission system according to claim 16, theelectric-to-optical signal converter including a multi-wavelengthsurface emitting laser.
 19. The data transmission system according toclaim 16, a transmission medium that transmits the second clock signaland the serial data being formed of a plurality of optical fibers, andthe electric-to-optical signal converter being formed of a multi-beamsurface emitting laser.
 20. The data transmission system according toclaim 15, the second data string including one or more unit data stringseach comprising a plurality of bits having a particular bit pattern. 21.The data transmission system according to claim 15, theserial-to-parallel conversion apparatus detecting the start position ofthe unit data string contained in the first data string in the serialdata based on the synchronization signal and samples the serial data insynchronization with the second clock signal without variably delayingthe serial data to convert the serial data into parallel data from oneunit data string to another.